1. Technical Field
The present invention relates to SRAM (Static Random Access Memory) cells and methods of forming the same, and more particularly, to SRAM cells having a landing pad in contact with upper and lower cell gate patterns and methods of forming the same.
2. Discussion of the Related Art
In semiconductor memory devices, a static random access memory (SRAM) device may offer advantages of lower power consumption and faster operating speed as compared to a dynamic random access memory (DRAM) device. Therefore, the SRAM may be widely used for cache memory in computer and/or other portable devices.
A unit cell of a SRAM device mat be categorized as either a resistor-load SRAM cell or a complementary metal-oxide semiconductor (CMOS) SRAM cell. A resistor-load SRAM cell may employ a high-resistance resistor as a load device, while a CMOS SRAM cell may employ a p-channel metal-oxide semiconductor (PMOS) transistor as a load device.
The CMOS SRAM cell may be categorized as one of two types. One type of CMOS SRAM cell is a thin film transistor (TFT) SRAM cell, which may employ TFTs stacked on a semiconductor substrate as the load device. The other is a bulk CMOS SRAM cell, which may employ bulk transistors formed on a semiconductor substrate as the load device.
The bulk CMOS SRAM cell may exhibit higher cell stability as compared to the TFT SRAM cell and the resistor-load SRAM cell. In other word, the bulk CMOS SRAM cell may have excellent low voltage characteristics and low stand-by current. This may be because the transistors that make up the bulk CMOS SRAM cell are typically formed of a single crystalline silicon substrate. In contrast, the TFTs of the TFT SRAM cell are typically formed using a polysilicon layer as a boby layer. However, the bulk CMOS SRAM cell may have lower integration density as well as weaker latch-up immunity as compared to the TFT SRAM cell. Therefore, in order to produce a highly integrated SRAM device having high reliability, characteristics of load transistors employed in the TFT SRAM cell may need to be improved.
In addition, each of the SRAM cells may include a pair of node contact structures. More particularly, in the TFT SRAM cell, each of the node contact structures may electrically connect a P-type drain region of a load transistor to an N-type drain region of a driver transistor.
U.S. Pat. No. 6,429,484 to Bin Yu (the '484 patent) discloses a multiple active layer structure and a method of making such a structure. According to the '484 patent, the structure and the method include a first layer having an oxide layer, a first active semiconductor layer and a first insulating layer, which are sequentially stacked. A second active layer is formed on the first insulating layer. The second active layer is recrystallized through a first seed window in the first insulating layer. A second insulating layer is formed on the second active layer.
The structure and the method further include a third active layer on the second insulating layer. The third active layer is recrystallized through a second seed window. The second seed window is aligned with the first seed window. At this time, at least one transistor is disposed in at least a portion of the first active layer. At least another transistor is formed in at least a portion of the second active layer. Further, at least still another transistor is formed in at least a portion of the third active layer.
However, the transistor is composed of a gate structure including a gate dielectric layer, a polysilicon conductive layer and spacers on sidewalls of the polysilicon conductive layer. At this time, the spacers and the active layers have different etch rates from one another. And each of the first and the second seed windows is formed adjacent to the spacer. Accordingly, the first seed window or the second seed window may increase in a probability of having different diameters from each other in an upper and a lower portions thereof due to the etch rate difference between the spacers and the active layers and due further to gradual reduction of a given design rule. Accordingly, the first seed window or the second seed window may have different diameters in the upper and lower portions thereof to deteriorate electrical characteristics of the structure.